METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a method for inhibiting excessive etching in the vicinity of a gate electrode. SOLUTION: An amorphous carbon layer 46 is formed on a substrate on which layers 43 and 44 to be etched are formed. A resist pattern 47 patterned in a predetermined region is formed on the...
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| creator | KOBAYASHI MASAHARU YAO TERUYOSHI HASHIMOTO KOICHI NAORI NOBUHISA OSHIMA MASASHI KAWAMURA EIICHI |
| description | PROBLEM TO BE SOLVED: To provide a method for inhibiting excessive etching in the vicinity of a gate electrode. SOLUTION: An amorphous carbon layer 46 is formed on a substrate on which layers 43 and 44 to be etched are formed. A resist pattern 47 patterned in a predetermined region is formed on the surface of the amorphous carbon layer 46. The amorphous carbon layer and the upper part of the layers to be patterned except at least the layer 43 of the lower part of the layers are etched by using the resist pattern 47 as a mask. Thereafter, the resist pattern 47 is removed. Furthermore, at least the layer 43 of the lower part of the layers to be patterned is etched selectively by using the amorphous carbon layer 46 as a mask. COPYRIGHT: (C)2007,JPO&INPIT |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2006303496A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2006303496A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2006303496A3</originalsourceid><addsrcrecordid>eNrjZND1dQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXCHb19XT293MJdQ4Byrm4hnk6u_IwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDAzNjA2MTSzNHY6IUAQAaHyYV</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>KOBAYASHI MASAHARU ; YAO TERUYOSHI ; HASHIMOTO KOICHI ; NAORI NOBUHISA ; OSHIMA MASASHI ; KAWAMURA EIICHI</creator><creatorcontrib>KOBAYASHI MASAHARU ; YAO TERUYOSHI ; HASHIMOTO KOICHI ; NAORI NOBUHISA ; OSHIMA MASASHI ; KAWAMURA EIICHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a method for inhibiting excessive etching in the vicinity of a gate electrode. SOLUTION: An amorphous carbon layer 46 is formed on a substrate on which layers 43 and 44 to be etched are formed. A resist pattern 47 patterned in a predetermined region is formed on the surface of the amorphous carbon layer 46. The amorphous carbon layer and the upper part of the layers to be patterned except at least the layer 43 of the lower part of the layers are etched by using the resist pattern 47 as a mask. Thereafter, the resist pattern 47 is removed. Furthermore, at least the layer 43 of the lower part of the layers to be patterned is etched selectively by using the amorphous carbon layer 46 as a mask. COPYRIGHT: (C)2007,JPO&INPIT</description><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20061102&DB=EPODOC&CC=JP&NR=2006303496A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20061102&DB=EPODOC&CC=JP&NR=2006303496A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KOBAYASHI MASAHARU</creatorcontrib><creatorcontrib>YAO TERUYOSHI</creatorcontrib><creatorcontrib>HASHIMOTO KOICHI</creatorcontrib><creatorcontrib>NAORI NOBUHISA</creatorcontrib><creatorcontrib>OSHIMA MASASHI</creatorcontrib><creatorcontrib>KAWAMURA EIICHI</creatorcontrib><title>METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a method for inhibiting excessive etching in the vicinity of a gate electrode. SOLUTION: An amorphous carbon layer 46 is formed on a substrate on which layers 43 and 44 to be etched are formed. A resist pattern 47 patterned in a predetermined region is formed on the surface of the amorphous carbon layer 46. The amorphous carbon layer and the upper part of the layers to be patterned except at least the layer 43 of the lower part of the layers are etched by using the resist pattern 47 as a mask. Thereafter, the resist pattern 47 is removed. Furthermore, at least the layer 43 of the lower part of the layers to be patterned is etched selectively by using the amorphous carbon layer 46 as a mask. COPYRIGHT: (C)2007,JPO&INPIT</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND1dQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXCHb19XT293MJdQ4Byrm4hnk6u_IwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDAzNjA2MTSzNHY6IUAQAaHyYV</recordid><startdate>20061102</startdate><enddate>20061102</enddate><creator>KOBAYASHI MASAHARU</creator><creator>YAO TERUYOSHI</creator><creator>HASHIMOTO KOICHI</creator><creator>NAORI NOBUHISA</creator><creator>OSHIMA MASASHI</creator><creator>KAWAMURA EIICHI</creator><scope>EVB</scope></search><sort><creationdate>20061102</creationdate><title>METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><author>KOBAYASHI MASAHARU ; YAO TERUYOSHI ; HASHIMOTO KOICHI ; NAORI NOBUHISA ; OSHIMA MASASHI ; KAWAMURA EIICHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2006303496A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KOBAYASHI MASAHARU</creatorcontrib><creatorcontrib>YAO TERUYOSHI</creatorcontrib><creatorcontrib>HASHIMOTO KOICHI</creatorcontrib><creatorcontrib>NAORI NOBUHISA</creatorcontrib><creatorcontrib>OSHIMA MASASHI</creatorcontrib><creatorcontrib>KAWAMURA EIICHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KOBAYASHI MASAHARU</au><au>YAO TERUYOSHI</au><au>HASHIMOTO KOICHI</au><au>NAORI NOBUHISA</au><au>OSHIMA MASASHI</au><au>KAWAMURA EIICHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><date>2006-11-02</date><risdate>2006</risdate><abstract>PROBLEM TO BE SOLVED: To provide a method for inhibiting excessive etching in the vicinity of a gate electrode. SOLUTION: An amorphous carbon layer 46 is formed on a substrate on which layers 43 and 44 to be etched are formed. A resist pattern 47 patterned in a predetermined region is formed on the surface of the amorphous carbon layer 46. The amorphous carbon layer and the upper part of the layers to be patterned except at least the layer 43 of the lower part of the layers are etched by using the resist pattern 47 as a mask. Thereafter, the resist pattern 47 is removed. Furthermore, at least the layer 43 of the lower part of the layers to be patterned is etched selectively by using the amorphous carbon layer 46 as a mask. COPYRIGHT: (C)2007,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES |
| title | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
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