CONTACT ARRANGEMENT SUITABLE FOR MEMORY ARRAY, AND MANUFACTURING METHOD THEREFOR

PROBLEM TO BE SOLVED: To provide a contact arrangement that can lower the resistance of a selective transistor line and a source line in a NAND type flash memory array, and its manufacturing method. SOLUTION: The manufacturing method for a contact arrangement includes the steps of forming a substrate on whose main surface 1 a tunnel dielectric layer 6 is stacked, wherein a first conductive line extends onto the tunnel dielectric layer 6 in a first direction and is set in place, stacking a dielectric material's layer to the first conductive line, stacking a control gate layer 10, patterning the first conductive line and forming a gate lamination layer 20, stacking dielectric materials between the gate lamination layer 20, partially removing the gate lamination layer 20 and exposing a floating gate electrode 9 in a region where a selective transistor line 24 is formed, thereby forming a selective transistor line groove 23 that extends in a second direction, and filling the selective transistor line groove 23 with a conductive material to form the selective transistor line 24. COPYRIGHT: (C)2007,JPO&INPIT