SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To balance the parasitic capacitance of the global data line pair of 3 transistor cells. SOLUTION: For a plurality of 1st memory cells, the gates of 1st and 2nd transistors are connected to one of a plurality of 1st word lines and the drain of a 3rd transistor is connected to the source/drain route of the 2nd transistor. For a plurality of 2nd memory cells, the gates of 4th and 5th transistors are connected to one of a plurality of 2nd word lines and the drain of a 6th transistor is connected to the source/drain route of the 5th transistor. The source/drain route of the 1st transistor of the 1st memory cell is connected to 1st wiring and the source/drain route of the 4th transistor of the 2nd memory cell is connected to 2nd wiring. The source/drain route of the 2nd transistor of the 1st memory cell is connected through a 1st switch to the 2nd wiring and the source/drain route of the 5th transistor of the 2nd memory cell is connected through a 2nd switch to the 1st wiring. COPYRIGHT: (C)2007,JPO&INPIT