CLOCK TREE STABILIZER AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve the following problems: a variation in delay of a clock signal is a crucial factor of a timing error for an operation of each functional block, and constituting the clock tree suppresses the variation in the delay caused by the clock signal itself, however, the variation in delay of the clock tree cell occurs when influenced by the voltage drop to the inserted clock tree cell and a fluctuation in power source caused by the power consumption in a periheral cell. SOLUTION: A clock tree stabilizer for automatically inserting a capacity cell 43 to the periphery of the clock tree cell is composed to the layout data 11 comprising the clock-tree. COPYRIGHT: (C)2006,JPO&NCIPI