SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To improve operation speed with low power consumption, avoiding the problem of leakage current at standby due to a sub-threshold current in a static memory that is operated with low voltage such as approximately 1V power supply voltage, and to secure a voltage margin of a memor...

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Bibliographische Detailangaben
Hauptverfasser: ITO KIYOO, ISHIBASHI KOICHIRO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To improve operation speed with low power consumption, avoiding the problem of leakage current at standby due to a sub-threshold current in a static memory that is operated with low voltage such as approximately 1V power supply voltage, and to secure a voltage margin of a memory cell of the static memory that decreases due to a drop of the power supply voltage. SOLUTION: In a static memory cell composed of cross-coupled MOS transistors having a relatively high threshold voltage, a MOS transistor for controlling the power feeder line voltage is provided. The power feeder voltage control transistor is turned on after a word line voltage is turned off for feeding a high voltage VCH to a feeder line, so that the voltage difference between two storage nodes in a memory cell in the non-selected state becomes larger than the voltage difference between the two nodes when a voltage corresponded to the write information is applied on the two nodes in a selected memory cell from data paired lines DL, /DL. COPYRIGHT: (C)2006,JPO&NCIPI