METHOD FOR TESTING INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a method for testing an integrated circuit capable of suppressing increase of test-use terminals becoming problematic when building a test system such as a scan path test, a boundary scan test or the like in the integrated circuit being an object to be tested. SOLUTION: Shift registers FF1, FF2 which input a reset signal TRST and a test clock signal TCLK as input data from the outside and carry out a shift operation based on an output OSCOUT of an internal oscillation circuit OSC, are disposed in the integrated circuit being the object to be tested. When all of parallel outputs of the shift registers become H, the integrated circuit is brought to be in its test mode, thereby omitting input terminals for the test mode. Furthermore, a test clock signal TCL is generated so as to have an actual clock waveform in the test mode, thereby eliminating the need to add a terminal for inputting data which set the test mode. COPYRIGHT: (C)2006,JPO&NCIPI