PROGRAMMABLE LOGIC ARRAY

PROBLEM TO BE SOLVED: To provide the programmable logic array whose delay time is shortened in response to an delayed input signal. SOLUTION: The programmable logic array includes an AND plane and an OR plane. The AND plane operates in synchronization with a clock signal and generates a logical product signal in response to a first input signal. When a second input signal is inputted after inputting the first input signal; the OR plane generates a first logical sum signal in response to a first logical product signal independent from the second input signal, generates a second logical sum signal in response to a second logical product signal dependent to the second input signal, and varies the first logical sum signal according to the logical state of the second input signal and the second logical sum signal. Consequently, the operation speed of the programmable logic array is made high in response to an input signal inputted lately and a standby electricity is reduced. COPYRIGHT: (C)2006,JPO&NCIPI