SIGNAL INSPECTION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a signal inspection circuit capable of performing the operation of inspecting whether a plurality of binary signals have a predetermined expectation value, and the operation of selecting and outputting a part of the plurality of inputted binary signals with a simple...

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Bibliographische Detailangaben
1. Verfasser: AKAMATSU MASASHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a signal inspection circuit capable of performing the operation of inspecting whether a plurality of binary signals have a predetermined expectation value, and the operation of selecting and outputting a part of the plurality of inputted binary signals with a simple structure, and a semiconductor memory device. SOLUTION: A 64-bit binary signal outputted from a memory part 1 is inputted to the logic circuits PF0-0 to PF7-7 of a first logic circuit 10 through input terminals T10-0 to T17-7. At logic circuit PFi-j (i and j demote integers of 0 to 7), the OR operation of an exclusive OR of the input signal and the expectation value signal EV of an input terminal group TIi-j, and the logical inversion signal of a selected signal SELi is performed. At a second logic circuit 20, the the AND operation of the output signals of the logical circuits PF0-j to PF7-j is performed. This logical product is logically inverted according to the value of the expectation value signal EV to be outputted to the output terminal TOj. COPYRIGHT: (C)2006,JPO&NCIPI