SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of testing whether data read out of a memory cell are correct and whether there is a deviation between the timing where the data are read out of the memory cell and outputted to the outside and the timing where a WAIT signal is canceled. SOLUTION: In a WAIT control circuit 125, when it is operated normally, the WAIT signal is disabled after a predetermined period elapses after a readout instruction is received or after a predetermined period elapses after self-refreshment is completed. A level decision circuit 180 generates a level decision signal EOR1 indicating whether a plurality of read-out data are all equal in logical level. A test result decision circuit 185 generates a test result signal TR1 indicating a normal operation wherein there is no deviation between the timing where the WAIT signal is disabled and the timing where the level decision signal EOR1 varies. COPYRIGHT: (C)2006,JPO&NCIPI