PROCESSOR SYSTEM

PROBLEM TO BE SOLVED: To prevent collision of data on a shared bus in switching a task. SOLUTION: The processor system comprises a plurality of CPU modules connected to the shared bus, a shared memory connected to the shared bus 1 and shared by all of the CPU modules, and a timer interrupt generating unit for generating a timer interrupt signal to the plurality of the CPU modules. When the plurality of the CPU modules share a same shared memory, and the task interrupt signal is simultaneously input to the plurality of the CPU modules, a timing for switching the task by each of CPU core parts 11 is delayed mutually so as to supply the task interrupt signal individually to the CPU core part 11 by delaying in an inside of each of the CPU modules. Thereby, possibility of conflict of the data on the shared bus 1 can be reduced while the data is being saved in the shared memory from a local memory in switching the task. COPYRIGHT: (C)2006,JPO&NCIPI