MEMORY DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: YANA KOUZEN, JANG SE AUG, PARK HYUNG-SOON, KIM WOO-JIN, HWANG EUNG-RIM, TEI DAIGU, KIM SEO-MIN, SOHN HYUNUL, KIM YOUNG-BOG
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator YANA KOUZEN
JANG SE AUG
PARK HYUNG-SOON
KIM WOO-JIN
HWANG EUNG-RIM
TEI DAIGU
KIM SEO-MIN
SOHN HYUNUL
KIM YOUNG-BOG
description PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold time of the memory device. SOLUTION: The memory device comprises a semiconductor substrate (610) with a recess (600) formed therein, a first junction region (670A) formed on a surface lower part of the semiconductor substrate in the recess, a plurality of second junction regions (670B) formed on a surface lower part of the semiconductor substrate outside the recess, gate structures (655) formed on the semiconductor substrate between the first and second junction regions, including at least a part of the gate structure formed on the semiconductor substrate in the recess, a first contact plug (690A) formed on the first junction region by burying between the gate structures, and a plurality of second plugs (690B) formed on the second junction regions by burying between the gate structures. COPYRIGHT: (C)2006,JPO&NCIPI
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2006041475A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2006041475A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2006041475A3</originalsourceid><addsrcrecordid>eNrjZNDydfX1D4pUcHEN83R2VXD0c1HwDAlW8HX0C3VzdA4JDfL0c1fwdQ3x8HfhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZmBiaGJuamjsZEKQIAj-IlAA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY DEVICE AND ITS MANUFACTURING METHOD</title><source>esp@cenet</source><creator>YANA KOUZEN ; JANG SE AUG ; PARK HYUNG-SOON ; KIM WOO-JIN ; HWANG EUNG-RIM ; TEI DAIGU ; KIM SEO-MIN ; SOHN HYUNUL ; KIM YOUNG-BOG</creator><creatorcontrib>YANA KOUZEN ; JANG SE AUG ; PARK HYUNG-SOON ; KIM WOO-JIN ; HWANG EUNG-RIM ; TEI DAIGU ; KIM SEO-MIN ; SOHN HYUNUL ; KIM YOUNG-BOG</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold time of the memory device. SOLUTION: The memory device comprises a semiconductor substrate (610) with a recess (600) formed therein, a first junction region (670A) formed on a surface lower part of the semiconductor substrate in the recess, a plurality of second junction regions (670B) formed on a surface lower part of the semiconductor substrate outside the recess, gate structures (655) formed on the semiconductor substrate between the first and second junction regions, including at least a part of the gate structure formed on the semiconductor substrate in the recess, a first contact plug (690A) formed on the first junction region by burying between the gate structures, and a plurality of second plugs (690B) formed on the second junction regions by burying between the gate structures. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060209&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006041475A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060209&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006041475A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YANA KOUZEN</creatorcontrib><creatorcontrib>JANG SE AUG</creatorcontrib><creatorcontrib>PARK HYUNG-SOON</creatorcontrib><creatorcontrib>KIM WOO-JIN</creatorcontrib><creatorcontrib>HWANG EUNG-RIM</creatorcontrib><creatorcontrib>TEI DAIGU</creatorcontrib><creatorcontrib>KIM SEO-MIN</creatorcontrib><creatorcontrib>SOHN HYUNUL</creatorcontrib><creatorcontrib>KIM YOUNG-BOG</creatorcontrib><title>MEMORY DEVICE AND ITS MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold time of the memory device. SOLUTION: The memory device comprises a semiconductor substrate (610) with a recess (600) formed therein, a first junction region (670A) formed on a surface lower part of the semiconductor substrate in the recess, a plurality of second junction regions (670B) formed on a surface lower part of the semiconductor substrate outside the recess, gate structures (655) formed on the semiconductor substrate between the first and second junction regions, including at least a part of the gate structure formed on the semiconductor substrate in the recess, a first contact plug (690A) formed on the first junction region by burying between the gate structures, and a plurality of second plugs (690B) formed on the second junction regions by burying between the gate structures. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDydfX1D4pUcHEN83R2VXD0c1HwDAlW8HX0C3VzdA4JDfL0c1fwdQ3x8HfhYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgZmBiaGJuamjsZEKQIAj-IlAA</recordid><startdate>20060209</startdate><enddate>20060209</enddate><creator>YANA KOUZEN</creator><creator>JANG SE AUG</creator><creator>PARK HYUNG-SOON</creator><creator>KIM WOO-JIN</creator><creator>HWANG EUNG-RIM</creator><creator>TEI DAIGU</creator><creator>KIM SEO-MIN</creator><creator>SOHN HYUNUL</creator><creator>KIM YOUNG-BOG</creator><scope>EVB</scope></search><sort><creationdate>20060209</creationdate><title>MEMORY DEVICE AND ITS MANUFACTURING METHOD</title><author>YANA KOUZEN ; JANG SE AUG ; PARK HYUNG-SOON ; KIM WOO-JIN ; HWANG EUNG-RIM ; TEI DAIGU ; KIM SEO-MIN ; SOHN HYUNUL ; KIM YOUNG-BOG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2006041475A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YANA KOUZEN</creatorcontrib><creatorcontrib>JANG SE AUG</creatorcontrib><creatorcontrib>PARK HYUNG-SOON</creatorcontrib><creatorcontrib>KIM WOO-JIN</creatorcontrib><creatorcontrib>HWANG EUNG-RIM</creatorcontrib><creatorcontrib>TEI DAIGU</creatorcontrib><creatorcontrib>KIM SEO-MIN</creatorcontrib><creatorcontrib>SOHN HYUNUL</creatorcontrib><creatorcontrib>KIM YOUNG-BOG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YANA KOUZEN</au><au>JANG SE AUG</au><au>PARK HYUNG-SOON</au><au>KIM WOO-JIN</au><au>HWANG EUNG-RIM</au><au>TEI DAIGU</au><au>KIM SEO-MIN</au><au>SOHN HYUNUL</au><au>KIM YOUNG-BOG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY DEVICE AND ITS MANUFACTURING METHOD</title><date>2006-02-09</date><risdate>2006</risdate><abstract>PROBLEM TO BE SOLVED: To provide a memory device and its manufacturing method which facilitates adjusting the threshold voltage of the memory device by preventing the short channel effect, and reduces the junction leakage current generated in a storage node junction region to increase the data hold time of the memory device. SOLUTION: The memory device comprises a semiconductor substrate (610) with a recess (600) formed therein, a first junction region (670A) formed on a surface lower part of the semiconductor substrate in the recess, a plurality of second junction regions (670B) formed on a surface lower part of the semiconductor substrate outside the recess, gate structures (655) formed on the semiconductor substrate between the first and second junction regions, including at least a part of the gate structure formed on the semiconductor substrate in the recess, a first contact plug (690A) formed on the first junction region by burying between the gate structures, and a plurality of second plugs (690B) formed on the second junction regions by burying between the gate structures. COPYRIGHT: (C)2006,JPO&amp;NCIPI</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2006041475A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title MEMORY DEVICE AND ITS MANUFACTURING METHOD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T10%3A41%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YANA%20KOUZEN&rft.date=2006-02-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2006041475A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true