METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: SHIMIZU TADAYOSHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SHIMIZU TADAYOSHI
description PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using it and a semiconductor device. SOLUTION: The method for forming the positioning mark 112 comprises steps of: flattening the surface of an insulating layer 105; forming a masking film 106 on the insulating layer 105; forming a first and a second pattern 107, 108 by etching a part of the masking film 106 and the insulating layer 105; forming a metallic film 109 covering the insulating layer 105 and the masking film 106; forming a third pattern 110 and a first interconnection pattern 111 by removing a portion of the metallic film 109; and protruding a portion of the third pattern 110 from the main surface of the insulating layer 105. COPYRIGHT: (C)2006,JPO&NCIPI
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2006032853A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2006032853A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2006032853A3</originalsourceid><addsrcrecordid>eNqNjcEKwjAQRHvxIOo_LJ4VSovSa0xSGyXZkmzqsRSJJ9FC_SN_1LZ4UPDgYZmFmXkzjZ5aUoECcrTDaWX2UKJTpNAMv2b2CMwIOCk7eoxIWgOlxUoJKQANOKkVRyM8p57i_M6RZSRX8MHWzPiccfIj5bshZKV4Hx9mfjnzaHJprl1YvHUWLXNJvFiH9l6Hrm3O4RYe9aFM4ngbp0m2SVn6V-gFLWdGrA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>SHIMIZU TADAYOSHI</creator><creatorcontrib>SHIMIZU TADAYOSHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using it and a semiconductor device. SOLUTION: The method for forming the positioning mark 112 comprises steps of: flattening the surface of an insulating layer 105; forming a masking film 106 on the insulating layer 105; forming a first and a second pattern 107, 108 by etching a part of the masking film 106 and the insulating layer 105; forming a metallic film 109 covering the insulating layer 105 and the masking film 106; forming a third pattern 110 and a first interconnection pattern 111 by removing a portion of the metallic film 109; and protruding a portion of the third pattern 110 from the main surface of the insulating layer 105. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060202&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006032853A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060202&amp;DB=EPODOC&amp;CC=JP&amp;NR=2006032853A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIMIZU TADAYOSHI</creatorcontrib><title>METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using it and a semiconductor device. SOLUTION: The method for forming the positioning mark 112 comprises steps of: flattening the surface of an insulating layer 105; forming a masking film 106 on the insulating layer 105; forming a first and a second pattern 107, 108 by etching a part of the masking film 106 and the insulating layer 105; forming a metallic film 109 covering the insulating layer 105 and the masking film 106; forming a third pattern 110 and a first interconnection pattern 111 by removing a portion of the metallic film 109; and protruding a portion of the third pattern 110 from the main surface of the insulating layer 105. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjcEKwjAQRHvxIOo_LJ4VSovSa0xSGyXZkmzqsRSJJ9FC_SN_1LZ4UPDgYZmFmXkzjZ5aUoECcrTDaWX2UKJTpNAMv2b2CMwIOCk7eoxIWgOlxUoJKQANOKkVRyM8p57i_M6RZSRX8MHWzPiccfIj5bshZKV4Hx9mfjnzaHJprl1YvHUWLXNJvFiH9l6Hrm3O4RYe9aFM4ngbp0m2SVn6V-gFLWdGrA</recordid><startdate>20060202</startdate><enddate>20060202</enddate><creator>SHIMIZU TADAYOSHI</creator><scope>EVB</scope></search><sort><creationdate>20060202</creationdate><title>METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE</title><author>SHIMIZU TADAYOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2006032853A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIMIZU TADAYOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIMIZU TADAYOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE</title><date>2006-02-02</date><risdate>2006</risdate><abstract>PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using it and a semiconductor device. SOLUTION: The method for forming the positioning mark 112 comprises steps of: flattening the surface of an insulating layer 105; forming a masking film 106 on the insulating layer 105; forming a first and a second pattern 107, 108 by etching a part of the masking film 106 and the insulating layer 105; forming a metallic film 109 covering the insulating layer 105 and the masking film 106; forming a third pattern 110 and a first interconnection pattern 111 by removing a portion of the metallic film 109; and protruding a portion of the third pattern 110 from the main surface of the insulating layer 105. COPYRIGHT: (C)2006,JPO&amp;NCIPI</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2006032853A
source esp@cenet
subjects APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
title METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T21%3A17%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHIMIZU%20TADAYOSHI&rft.date=2006-02-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2006032853A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true