METHOD FOR FORMING POSITIONING MARK AND WIRING PATTERN PROVIDED ON SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using...

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Bibliographische Detailangaben
1. Verfasser: SHIMIZU TADAYOSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a method for forming a positioning mark and an interconnection pattern forming a fine interconnection pattern to form the positioning mark, which are easily recongnized at a step of exposure, and also to provide a method for manufacturing a semiconductor device using it and a semiconductor device. SOLUTION: The method for forming the positioning mark 112 comprises steps of: flattening the surface of an insulating layer 105; forming a masking film 106 on the insulating layer 105; forming a first and a second pattern 107, 108 by etching a part of the masking film 106 and the insulating layer 105; forming a metallic film 109 covering the insulating layer 105 and the masking film 106; forming a third pattern 110 and a first interconnection pattern 111 by removing a portion of the metallic film 109; and protruding a portion of the third pattern 110 from the main surface of the insulating layer 105. COPYRIGHT: (C)2006,JPO&NCIPI