METHOD AND APPARATUS FOR TIMING ANALYSIS

PROBLEM TO BE SOLVED: To provide a method and apparatus for timing analysis of an LSI based on a design margin reflecting a plurality of manufacturing variation factors and delay error variation. SOLUTION: A timing analysis apparatus 101 reads a net list 103 including connection information of an LSI circuit cell, a delay data 102 having delay information of the circuit cell stored in advance, a number of stages-derating factor dependence 104 and a derating factor (PVT) 107. A detection means 106 for detecting the number of cell stages of a signal path detects the number of stages of the signal path, decides a derating factor indicating a degree of averaging random variation according to the number of stages of the signal path, and performs timing analysis based on the above degree. Thus, accurate timing design can be performed for a large scale circuit conforming to an actual situation. COPYRIGHT: (C)2006,JPO&NCIPI