LAMINATE FOR FORMING WIRING BOARD, ITS MANUFACTURING METHOD AND WIRING BOARD
PROBLEM TO BE SOLVED: To provide a laminate for forming a wiring board excellent in adhesion and low in resistance, a laminate manufacturing method, and the highly detailed wiring board of high reliability obtained from the laminate. SOLUTION: The laminate for forming the wiring board is constituted...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | HIRUMA TAKEHIKO |
| description | PROBLEM TO BE SOLVED: To provide a laminate for forming a wiring board excellent in adhesion and low in resistance, a laminate manufacturing method, and the highly detailed wiring board of high reliability obtained from the laminate. SOLUTION: The laminate for forming the wiring board is constituted so that a substrate layer based on an Ni-Mo alloy and a conductor layer based on Al or an Al alloy are probided on a substrate and the substrate layer contains oxygen and/or nitrogen. The manufacturing method of the laminate by a sputtering method and the wiring board formed by etching the laminate are also disclosed. COPYRIGHT: (C)2006,JPO&NCIPI |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2005305714A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2005305714A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2005305714A3</originalsourceid><addsrcrecordid>eNrjZPDxcfT19HMMcVVw8w8CYSDPXSHcMwhEOfk7BrnoKHiGBCv4OvqFujk6h4SCJXxdQzz8XRQc_VxQlPIwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDA1NjA1NzQxNHY6IUAQD0Vi4V</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>LAMINATE FOR FORMING WIRING BOARD, ITS MANUFACTURING METHOD AND WIRING BOARD</title><source>esp@cenet</source><creator>HIRUMA TAKEHIKO</creator><creatorcontrib>HIRUMA TAKEHIKO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a laminate for forming a wiring board excellent in adhesion and low in resistance, a laminate manufacturing method, and the highly detailed wiring board of high reliability obtained from the laminate. SOLUTION: The laminate for forming the wiring board is constituted so that a substrate layer based on an Ni-Mo alloy and a conductor layer based on Al or an Al alloy are probided on a substrate and the substrate layer contains oxygen and/or nitrogen. The manufacturing method of the laminate by a sputtering method and the wiring board formed by etching the laminate are also disclosed. COPYRIGHT: (C)2006,JPO&NCIPI</description><edition>7</edition><language>eng</language><subject>ADVERTISING ; BASIC ELECTRIC ELEMENTS ; CRYPTOGRAPHY ; DISPLAY ; DISPLAYING ; EDUCATION ; ELECTRIC HEATING ; ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; LABELS OR NAME-PLATES ; LAYERED PRODUCTS ; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM ; PERFORMING OPERATIONS ; PHYSICS ; SEALS ; SEMICONDUCTOR DEVICES ; SIGNS ; TRANSPORTING</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051104&DB=EPODOC&CC=JP&NR=2005305714A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20051104&DB=EPODOC&CC=JP&NR=2005305714A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRUMA TAKEHIKO</creatorcontrib><title>LAMINATE FOR FORMING WIRING BOARD, ITS MANUFACTURING METHOD AND WIRING BOARD</title><description>PROBLEM TO BE SOLVED: To provide a laminate for forming a wiring board excellent in adhesion and low in resistance, a laminate manufacturing method, and the highly detailed wiring board of high reliability obtained from the laminate. SOLUTION: The laminate for forming the wiring board is constituted so that a substrate layer based on an Ni-Mo alloy and a conductor layer based on Al or an Al alloy are probided on a substrate and the substrate layer contains oxygen and/or nitrogen. The manufacturing method of the laminate by a sputtering method and the wiring board formed by etching the laminate are also disclosed. COPYRIGHT: (C)2006,JPO&NCIPI</description><subject>ADVERTISING</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CRYPTOGRAPHY</subject><subject>DISPLAY</subject><subject>DISPLAYING</subject><subject>EDUCATION</subject><subject>ELECTRIC HEATING</subject><subject>ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>LABELS OR NAME-PLATES</subject><subject>LAYERED PRODUCTS</subject><subject>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</subject><subject>PERFORMING OPERATIONS</subject><subject>PHYSICS</subject><subject>SEALS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SIGNS</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPDxcfT19HMMcVVw8w8CYSDPXSHcMwhEOfk7BrnoKHiGBCv4OvqFujk6h4SCJXxdQzz8XRQc_VxQlPIwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDA1NjA1NzQxNHY6IUAQD0Vi4V</recordid><startdate>20051104</startdate><enddate>20051104</enddate><creator>HIRUMA TAKEHIKO</creator><scope>EVB</scope></search><sort><creationdate>20051104</creationdate><title>LAMINATE FOR FORMING WIRING BOARD, ITS MANUFACTURING METHOD AND WIRING BOARD</title><author>HIRUMA TAKEHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2005305714A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>ADVERTISING</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CRYPTOGRAPHY</topic><topic>DISPLAY</topic><topic>DISPLAYING</topic><topic>EDUCATION</topic><topic>ELECTRIC HEATING</topic><topic>ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>LABELS OR NAME-PLATES</topic><topic>LAYERED PRODUCTS</topic><topic>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</topic><topic>PERFORMING OPERATIONS</topic><topic>PHYSICS</topic><topic>SEALS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SIGNS</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>HIRUMA TAKEHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIRUMA TAKEHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LAMINATE FOR FORMING WIRING BOARD, ITS MANUFACTURING METHOD AND WIRING BOARD</title><date>2005-11-04</date><risdate>2005</risdate><abstract>PROBLEM TO BE SOLVED: To provide a laminate for forming a wiring board excellent in adhesion and low in resistance, a laminate manufacturing method, and the highly detailed wiring board of high reliability obtained from the laminate. SOLUTION: The laminate for forming the wiring board is constituted so that a substrate layer based on an Ni-Mo alloy and a conductor layer based on Al or an Al alloy are probided on a substrate and the substrate layer contains oxygen and/or nitrogen. The manufacturing method of the laminate by a sputtering method and the wiring board formed by etching the laminate are also disclosed. COPYRIGHT: (C)2006,JPO&NCIPI</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JP2005305714A |
| source | esp@cenet |
| subjects | ADVERTISING BASIC ELECTRIC ELEMENTS CRYPTOGRAPHY DISPLAY DISPLAYING EDUCATION ELECTRIC HEATING ELECTRIC LIGHTING NOT OTHERWISE PROVIDED FOR ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY LABELS OR NAME-PLATES LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM PERFORMING OPERATIONS PHYSICS SEALS SEMICONDUCTOR DEVICES SIGNS TRANSPORTING |
| title | LAMINATE FOR FORMING WIRING BOARD, ITS MANUFACTURING METHOD AND WIRING BOARD |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T22%3A45%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HIRUMA%20TAKEHIKO&rft.date=2005-11-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2005305714A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |