CHIP CAPACITOR MOUNTING STRUCTURE AND PRINTED WIRING BOARD

PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. SOLUTION: As a mounting structure for c...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MATSUMOTO TAKASHI, KAWADA ATSUMI, TAKAHIRA MITSURU, MIZOE YUKIO, TSUNODA ATSUSHI, KAMISAKA AKIRA, ONO TAKAYUKI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MATSUMOTO TAKASHI
KAWADA ATSUMI
TAKAHIRA MITSURU
MIZOE YUKIO
TSUNODA ATSUSHI
KAMISAKA AKIRA
ONO TAKAYUKI
description PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. SOLUTION: As a mounting structure for connecting a chip capacitor 3 by solder on the power source of the backside of the mounting place of a printed wiring board connecting the BGA package 1 by solder and a through-hole pad for ground, the circuit connection distance of the power source and the ground is made shorter than that in a conventional structure. Consequently, resistance and inductance of wiring can be reduced and the power source and ground noise can be reduced. Furthermore, since mounting of the chip capacitor on an area near the BGA package in a conventional structure is eliminated, an area required for chip capacitor mounting can be greatly reduced. COPYRIGHT: (C)2006,JPO&NCIPI
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2005277115A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2005277115A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2005277115A3</originalsourceid><addsrcrecordid>eNrjZLBy9vAMUHB2DHB09gzxD1Lw9Q_1C_H0c1cIDgkKdQ4JDXJVcPRzUQgI8vQLcXVRCPcMAkk6-TsGufAwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDA1Mjc3NDQ1NHY6IUAQATnimO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CHIP CAPACITOR MOUNTING STRUCTURE AND PRINTED WIRING BOARD</title><source>esp@cenet</source><creator>MATSUMOTO TAKASHI ; KAWADA ATSUMI ; TAKAHIRA MITSURU ; MIZOE YUKIO ; TSUNODA ATSUSHI ; KAMISAKA AKIRA ; ONO TAKAYUKI</creator><creatorcontrib>MATSUMOTO TAKASHI ; KAWADA ATSUMI ; TAKAHIRA MITSURU ; MIZOE YUKIO ; TSUNODA ATSUSHI ; KAMISAKA AKIRA ; ONO TAKAYUKI</creatorcontrib><description>PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. SOLUTION: As a mounting structure for connecting a chip capacitor 3 by solder on the power source of the backside of the mounting place of a printed wiring board connecting the BGA package 1 by solder and a through-hole pad for ground, the circuit connection distance of the power source and the ground is made shorter than that in a conventional structure. Consequently, resistance and inductance of wiring can be reduced and the power source and ground noise can be reduced. Furthermore, since mounting of the chip capacitor on an area near the BGA package in a conventional structure is eliminated, an area required for chip capacitor mounting can be greatly reduced. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20051006&amp;DB=EPODOC&amp;CC=JP&amp;NR=2005277115A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20051006&amp;DB=EPODOC&amp;CC=JP&amp;NR=2005277115A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUMOTO TAKASHI</creatorcontrib><creatorcontrib>KAWADA ATSUMI</creatorcontrib><creatorcontrib>TAKAHIRA MITSURU</creatorcontrib><creatorcontrib>MIZOE YUKIO</creatorcontrib><creatorcontrib>TSUNODA ATSUSHI</creatorcontrib><creatorcontrib>KAMISAKA AKIRA</creatorcontrib><creatorcontrib>ONO TAKAYUKI</creatorcontrib><title>CHIP CAPACITOR MOUNTING STRUCTURE AND PRINTED WIRING BOARD</title><description>PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. SOLUTION: As a mounting structure for connecting a chip capacitor 3 by solder on the power source of the backside of the mounting place of a printed wiring board connecting the BGA package 1 by solder and a through-hole pad for ground, the circuit connection distance of the power source and the ground is made shorter than that in a conventional structure. Consequently, resistance and inductance of wiring can be reduced and the power source and ground noise can be reduced. Furthermore, since mounting of the chip capacitor on an area near the BGA package in a conventional structure is eliminated, an area required for chip capacitor mounting can be greatly reduced. COPYRIGHT: (C)2006,JPO&amp;NCIPI</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBy9vAMUHB2DHB09gzxD1Lw9Q_1C_H0c1cIDgkKdQ4JDXJVcPRzUQgI8vQLcXVRCPcMAkk6-TsGufAwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDA1Mjc3NDQ1NHY6IUAQATnimO</recordid><startdate>20051006</startdate><enddate>20051006</enddate><creator>MATSUMOTO TAKASHI</creator><creator>KAWADA ATSUMI</creator><creator>TAKAHIRA MITSURU</creator><creator>MIZOE YUKIO</creator><creator>TSUNODA ATSUSHI</creator><creator>KAMISAKA AKIRA</creator><creator>ONO TAKAYUKI</creator><scope>EVB</scope></search><sort><creationdate>20051006</creationdate><title>CHIP CAPACITOR MOUNTING STRUCTURE AND PRINTED WIRING BOARD</title><author>MATSUMOTO TAKASHI ; KAWADA ATSUMI ; TAKAHIRA MITSURU ; MIZOE YUKIO ; TSUNODA ATSUSHI ; KAMISAKA AKIRA ; ONO TAKAYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2005277115A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUMOTO TAKASHI</creatorcontrib><creatorcontrib>KAWADA ATSUMI</creatorcontrib><creatorcontrib>TAKAHIRA MITSURU</creatorcontrib><creatorcontrib>MIZOE YUKIO</creatorcontrib><creatorcontrib>TSUNODA ATSUSHI</creatorcontrib><creatorcontrib>KAMISAKA AKIRA</creatorcontrib><creatorcontrib>ONO TAKAYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUMOTO TAKASHI</au><au>KAWADA ATSUMI</au><au>TAKAHIRA MITSURU</au><au>MIZOE YUKIO</au><au>TSUNODA ATSUSHI</au><au>KAMISAKA AKIRA</au><au>ONO TAKAYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CHIP CAPACITOR MOUNTING STRUCTURE AND PRINTED WIRING BOARD</title><date>2005-10-06</date><risdate>2005</risdate><abstract>PROBLEM TO BE SOLVED: To reduce a power supply and ground noise caused by high performance and high frequency of a semiconductor device with a BGA package mounted on a printed wiring board, and to reduce a chip capacitor mounting area used for noise reduction. SOLUTION: As a mounting structure for connecting a chip capacitor 3 by solder on the power source of the backside of the mounting place of a printed wiring board connecting the BGA package 1 by solder and a through-hole pad for ground, the circuit connection distance of the power source and the ground is made shorter than that in a conventional structure. Consequently, resistance and inductance of wiring can be reduced and the power source and ground noise can be reduced. Furthermore, since mounting of the chip capacitor on an area near the BGA package in a conventional structure is eliminated, an area required for chip capacitor mounting can be greatly reduced. COPYRIGHT: (C)2006,JPO&amp;NCIPI</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2005277115A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE
title CHIP CAPACITOR MOUNTING STRUCTURE AND PRINTED WIRING BOARD
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T19%3A04%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATSUMOTO%20TAKASHI&rft.date=2005-10-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2005277115A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true