LAYOUT VERIFICATION METHOD AND LAYOUT VERIFICATION PROGRAM

PROBLEM TO BE SOLVED: To attain the layout verification of first and second semiconductor chips configuring a multi-chip module in order to satisfy predetermined specifications as a whole multi-chip module. SOLUTION: This layout verification method for performing layout verification for a multi-chip module where a first semiconductor chip and a second semiconductor chip are vertically mounted is provided to convert a layout layer to be used by circuit layout data for the second semiconductor chip into a layout layer which is not used by the circuit layout data for the first semiconductor chip, and to form circuit layout data as one multi-chip module by the circuit layout data for the second semiconductor chip after conversion, the circuit layout data for the first semiconductor chip and connection data for connecting the first semiconductor chip with the second semiconductor chip, and to execute layout verification for the circuit layout data for one multi-chip module. COPYRIGHT: (C)2006,JPO&NCIPI