TIMING ANALYSIS METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To solve the following problem of hold time verification between registers: variation of a clock delay time is set as a design margin from a statistical delay error of simulation and an actual device, and clock delay becomes large to increase the design margin or design man-hours, and a chip size. SOLUTION: Clock input terminals of flip-flops in the preceding stage and the following stage are traced back to specify a branch point of a clock signal in step S1, delay from the clock branch point to the clock input terminal of the flip-flop in the following stage is found in step S2, and the statistical error of the simulation and the actual device is imparted to the delay as the margin in step S3. Because the delay error is small when having the same cell structure and when a difference of a voltage drop ratio or a wiring occupation ratio is small, the design margins of wiring and each cell are dynamically reduced, i.e., in each chip in step S5, S6, S6, and a hold time is checked in step S11. COPYRIGHT: (C)2006,JPO&NCIPI