PACKAGING DESIGN DEVICE AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a design system capable of proposing a design pattern employing a low power consumption flip-flop while preventing the deterioration of a target machine cycle (delay). SOLUTION: In designing of a semiconductor integrated circuit having a plurality of types of flip-flops that are the same in logical function and different in power consumption and delay characteristics, there are provided a two-stage path delay calculation means for performing delay calculation for both of a path from a flip-flop of interest to a flip-flop at the preceding stage and a path to a flip-flop at the following stage; a means for calculating the preceding-stage path delay and the following-stage path delay, and the amount of change in power consumption resulting from switching of the flip-flops by using the results of the two-stage path delay calculation; and a means for switching the flip-flops by determining a reference value of the delay or power consumption. COPYRIGHT: (C)2005,JPO&NCIPI