SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To enable data transfer without lowering a transfer rate when a combination of a master and a slave on a part-mounted board disables data communication, in synchronous serial communication between a master and a slave. SOLUTION: A semiconductor integrated circuit has a timing setting means (SSCR2) capable of setting the assertion timing and negation timing of a chip select signal, and a retiming means 80 capable of changing the assertion timing and negation timing of the chip select signal in relation to a transfer clock signal according to the setting content. The retiming means changes the assertion timing and negation timing of the chip select signal in relation to the transfer clock signal according to the setting content of the timing setting means. The change meets specifications of major signals to enable data communication without lowering the frequency of the transfer clock signal. COPYRIGHT: (C)2005,JPO&NCIPI