SCAN TEST METHOD, INTEGRATED CIRCUIT AND SCAN TEST CIRCUIT

PROBLEM TO BE SOLVED: To provide a scan test method for reducing the number of test patterns (the number of clocks), memory capacity and a processing period of time required for a scan test. SOLUTION: This method performs a scan test of an integrated circuit 1 provided with combinational circuits 10, 11, 12 and a flip-flop constituting a scan chain 20. The method performs an initial input step of setting a test initial value to the flip-flop using a serial scan input. Next, the method performs a capture operation step of capturing the value of the flip-flop to the other flip-flop through the combinational circuits 10, 11, 12, and a feeding back input shift step of feeding back and inputting an output value from the scan chain 20 to the input side of the scan chain 20 when performing a shift operation in the scan chain 20 alternately and repeatedly. Next, the method performs a collation step of collating the output value from the scan chain 20 with the expected value thereof. COPYRIGHT: (C)2005,JPO&NCIPI