DATA PROCESSOR

PROBLEM TO BE SOLVED: To give flexibility to a replacement object of an address translation counterpart in an address translation mechanism. SOLUTION: This data processor for supporting a virtual memory has a buffer memory (1) consisting of four-way set associative type cache memory provided with st...

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Bibliographische Detailangaben
Hauptverfasser: KAWASAKI IKUYA, TAMAKI SANEAKI, NARITA SUSUMU, YOSHIOKA SHINICHI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To give flexibility to a replacement object of an address translation counterpart in an address translation mechanism. SOLUTION: This data processor for supporting a virtual memory has a buffer memory (1) consisting of four-way set associative type cache memory provided with storage areas for storing correspondence information between logical page numbers (VPN) and physical page numbers (PPN), respectively, having a plurality of banks (11 to 14) having their index addresses shared, when storage information should be replaced from among the plurality of banks by the occurrence of cache mistakes, etc., a set to be replaced is optionally specified by execution of software by a central processor. For example, two-bit information for optionally specifying the bank is set in a register (MMUCR. RC). Signals (BSK1 to BSL4) for selecting one of the four banks are formed by decoding of a value set in the register. COPYRIGHT: (C)2005,JPO&NCIPI