CMOS GATE CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTED CHIP, SEMICONDUCTOR DEVICE, AND LOGIC PROCESSOR

PROBLEM TO BE SOLVED: To obtain a CMOS gate circuit which has simple configuration and whose off-leak current can easily be reduced. SOLUTION: The CMOS gate circuit is provided with a voltage reducing circuit which operates synchronously with at least one of a p-channel MOS transistor 1 and an n-channel MOS transistor 2, e.g. the transistor 2 while connected in series with the transistor 2 while the transistor 2 itself is turned off. Specifically, when a parallel connection body of an n-channel MOS transistor 3 and a p-channel MOS transistor 4 is provided, the source-drain voltage of an nMOS 2 becomes small as much as the source-side voltage of the nMOS 2 is raised by a threshold voltage Vth+α from a ground level, thereby reducing the off-leak current. COPYRIGHT: (C)2005,JPO&NCIPI