SEMICONDUCTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY DEVICE, AND PROJECTOR

PROBLEM TO BE SOLVED: To miniaturize the size of a semiconductor substrate by improving the layout of pixel cells. SOLUTION: The respective pixel cells are constituted of pixel switches M 20 to M 23 selected by gate lines, pixel electrodes into which image data is written from data lines D 20 and D...

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Bibliographische Detailangaben
1. Verfasser:	ORII TOSHIHIKO
Format:	Patent
Sprache:	eng
Schlagworte:	ACCESSORIES THEREFOR ADVERTISING APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USINGWAVES OTHER THAN OPTICAL WAVES APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FORPROJECTING OR VIEWING THEM CINEMATOGRAPHY CRYPTOGRAPHY DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING DISPLAY DISPLAYING EDUCATION ELECTROGRAPHY FREQUENCY-CHANGING HOLOGRAPHY LABELS OR NAME-PLATES NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHOTOGRAPHY PHYSICS SEALS SIGNS TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To miniaturize the size of a semiconductor substrate by improving the layout of pixel cells. SOLUTION: The respective pixel cells are constituted of pixel switches M 20 to M 23 selected by gate lines, pixel electrodes into which image data is written from data lines D 20 and D 21 through the selected pixel switches, and pixel capacitors CS 20 to CS 23 which are connected to the pixel switches and hold the image data. The pixel cells, one pair of which is arranged symmetrically with a horizontal scanning direction as one unit, are arranged in a matrix form. The boundaries between the pixel capacitors adjacent to each other in a vertical scanning direction are made of the same arrangement in all the pixel cells. Also, the pixel cells, one pair of which are arranged symmetrically with the vertical scanning direction as one unit, are arranged in the matrix form and the data lines D 20 and D 21 connected to the drains D of the transistors constituting the respective pixel switches are wired adjacently in parallel to each other and are always driven at the same timing. COPYRIGHT: (C)2005,JPO&NCIPI