SEMICONDUCTOR STORAGE DEVICE AND MICROCOMPUTER

PROBLEM TO BE SOLVED: To minimize an increase of a chip area caused by the addition of an ECC (Error Check and Correct) function. SOLUTION: When a semiconductor storage device includes; a memory mat section (10) in which a plurality of memory mats which are accessed in the largest bit width unit in the valid bit width modifiable according to designation from outside have been arranged and; an indirect peripheral circuit (20) shared with the plurality of memory mats, the indirect peripheral circuit is structured by including an ECC function block circuit (21) for error correction based on a hamming code and a data size alignment circuit (23) which performs data size alignment process according to the valid bit width specified from the outside. A bit configuration of a test mat is reduced by enabling an access to a memory mat with the largest bit width unit in a valid bit width modifiable according to a designation from the outside by setting a data size alignment circuit in a direct peripheral circuit. COPYRIGHT: (C)2005,JPO&NCIPI