CACHE MEMORY DEVICE
PROBLEM TO BE SOLVED: To provide a cache memory device whose performance is enhanced by letting the device accept subsequent access during the process of invalidating a cache memory. SOLUTION: The cache memory device has a control circuit which determines subsequent access as a cache error during th...
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a cache memory device whose performance is enhanced by letting the device accept subsequent access during the process of invalidating a cache memory. SOLUTION: The cache memory device has a control circuit which determines subsequent access as a cache error during the invalidation process based on the fact that access immediately after invalidation always results in a cache error, and which can store in the cache memory the data read by an external bus access, after starting the external bus access and making sure that the invalidation is complete. The external bus access of the subsequent access invalidated can be performed while the invalidation is being executed. To invalidate the cache memory having valid bits for retaining the effectiveness of each line, the valid bits need to be cleared for each line. This solves the problem with a conventional cache memory wherein a CPU needs to be stalled for the duration of the invalidation process because access cannot be accepted while the invalidation is being executed. COPYRIGHT: (C)2005,JPO&NCIPI |
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