SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a narrow-pitch wire bonding technique that can be applied to an LSI having a laminated wiring structure formed of Cu wiring and a low-k material similarly to an LSI having the conventional aluminum wiring by reducing the damages given to bonding pads. SOLUTION: In a...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | NAKAJIMA YASUYUKI MATSUZAWA ASAO TANAKA TADAYOSHI IWASAKI TOMIO MIURA HIDEO |
description | PROBLEM TO BE SOLVED: To provide a narrow-pitch wire bonding technique that can be applied to an LSI having a laminated wiring structure formed of Cu wiring and a low-k material similarly to an LSI having the conventional aluminum wiring by reducing the damages given to bonding pads. SOLUTION: In a semiconductor element in which multilayered laminated wiring is formed of Cu wiring and the low-k insulating film material, all cap wires to the uppermost cap wire are formed of Cu wiring layers. Each bonding pad formed of a Cu layer is constituted in a bonding pad structure in which a high-melting point intermediate metallic layer composed of a Ti (titanium) film or tungsten film, etc., is formed on the Cu layer, and an aluminum alloy layer is formed on the metallic layer. COPYRIGHT: (C)2005,JPO&NCIPI |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2005019493A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2005019493A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2005019493A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBqYGhpYmlsaOxkQpAgC9iR8g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>NAKAJIMA YASUYUKI ; MATSUZAWA ASAO ; TANAKA TADAYOSHI ; IWASAKI TOMIO ; MIURA HIDEO</creator><creatorcontrib>NAKAJIMA YASUYUKI ; MATSUZAWA ASAO ; TANAKA TADAYOSHI ; IWASAKI TOMIO ; MIURA HIDEO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a narrow-pitch wire bonding technique that can be applied to an LSI having a laminated wiring structure formed of Cu wiring and a low-k material similarly to an LSI having the conventional aluminum wiring by reducing the damages given to bonding pads. SOLUTION: In a semiconductor element in which multilayered laminated wiring is formed of Cu wiring and the low-k insulating film material, all cap wires to the uppermost cap wire are formed of Cu wiring layers. Each bonding pad formed of a Cu layer is constituted in a bonding pad structure in which a high-melting point intermediate metallic layer composed of a Ti (titanium) film or tungsten film, etc., is formed on the Cu layer, and an aluminum alloy layer is formed on the metallic layer. COPYRIGHT: (C)2005,JPO&NCIPI</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050120&DB=EPODOC&CC=JP&NR=2005019493A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20050120&DB=EPODOC&CC=JP&NR=2005019493A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAKAJIMA YASUYUKI</creatorcontrib><creatorcontrib>MATSUZAWA ASAO</creatorcontrib><creatorcontrib>TANAKA TADAYOSHI</creatorcontrib><creatorcontrib>IWASAKI TOMIO</creatorcontrib><creatorcontrib>MIURA HIDEO</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a narrow-pitch wire bonding technique that can be applied to an LSI having a laminated wiring structure formed of Cu wiring and a low-k material similarly to an LSI having the conventional aluminum wiring by reducing the damages given to bonding pads. SOLUTION: In a semiconductor element in which multilayered laminated wiring is formed of Cu wiring and the low-k insulating film material, all cap wires to the uppermost cap wire are formed of Cu wiring layers. Each bonding pad formed of a Cu layer is constituted in a bonding pad structure in which a high-melting point intermediate metallic layer composed of a Ti (titanium) film or tungsten film, etc., is formed on the Cu layer, and an aluminum alloy layer is formed on the metallic layer. COPYRIGHT: (C)2005,JPO&NCIPI</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBqYGhpYmlsaOxkQpAgC9iR8g</recordid><startdate>20050120</startdate><enddate>20050120</enddate><creator>NAKAJIMA YASUYUKI</creator><creator>MATSUZAWA ASAO</creator><creator>TANAKA TADAYOSHI</creator><creator>IWASAKI TOMIO</creator><creator>MIURA HIDEO</creator><scope>EVB</scope></search><sort><creationdate>20050120</creationdate><title>SEMICONDUCTOR DEVICE</title><author>NAKAJIMA YASUYUKI ; MATSUZAWA ASAO ; TANAKA TADAYOSHI ; IWASAKI TOMIO ; MIURA HIDEO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2005019493A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NAKAJIMA YASUYUKI</creatorcontrib><creatorcontrib>MATSUZAWA ASAO</creatorcontrib><creatorcontrib>TANAKA TADAYOSHI</creatorcontrib><creatorcontrib>IWASAKI TOMIO</creatorcontrib><creatorcontrib>MIURA HIDEO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAKAJIMA YASUYUKI</au><au>MATSUZAWA ASAO</au><au>TANAKA TADAYOSHI</au><au>IWASAKI TOMIO</au><au>MIURA HIDEO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2005-01-20</date><risdate>2005</risdate><abstract>PROBLEM TO BE SOLVED: To provide a narrow-pitch wire bonding technique that can be applied to an LSI having a laminated wiring structure formed of Cu wiring and a low-k material similarly to an LSI having the conventional aluminum wiring by reducing the damages given to bonding pads. SOLUTION: In a semiconductor element in which multilayered laminated wiring is formed of Cu wiring and the low-k insulating film material, all cap wires to the uppermost cap wire are formed of Cu wiring layers. Each bonding pad formed of a Cu layer is constituted in a bonding pad structure in which a high-melting point intermediate metallic layer composed of a Ti (titanium) film or tungsten film, etc., is formed on the Cu layer, and an aluminum alloy layer is formed on the metallic layer. COPYRIGHT: (C)2005,JPO&NCIPI</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_JP2005019493A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICE |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T12%3A57%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAKAJIMA%20YASUYUKI&rft.date=2005-01-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2005019493A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |