METHOD FOR FILLING UP SEPARATION STRUCTURE HAVING HIGH ASPECT RATIO WITH MATERIAL BASED ON POLYSILAZANE

PROBLEM TO BE SOLVED: To provide a method for filling up a separation trench in a silicon integrated circuit having at least one p-n junction or a phase boundary of different materials before forming a separation structure. SOLUTION: This method relates to filling of the separation trench and a capa...

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Hauptverfasser: ECONOMIKOS LAERTIS, DIVAKARUNI RAMA, JAMMY RAJARAO, SHAFER PADRAIC C, BELYANSKY MICHAEL P, SETTLEMYER JR KENNETH T
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a method for filling up a separation trench in a silicon integrated circuit having at least one p-n junction or a phase boundary of different materials before forming a separation structure. SOLUTION: This method relates to filling of the separation trench and a capacitor trench including a perpendicular field-effect transistor (FET) having aspect ratios up to a maximum of 60 (or p-n junction at an arbitrary front level or the phase boundary of the different materials) obtained through a process. The process comprises a step of coating a spin-on material based on silazane with low molecular weight, a step of performing prebake of the coated material at temperature less than about 450°C within oxygen atmosphere, a step of converting the stress of the material by heating within H2O atmosphere at intermediate temperature in the range from 450°C-800°C, a step of obtaining a material stable up to a maximum of 1000°C, which has compressive stress which can be adjusted by changing process parameters resulting from heating again within O2atmosphere at high temperature, and which has durability sufficiently resisting to CMP having an etching rate comparable to that of oxide dielectrics formed using the high-density plasma (HDP) technique. COPYRIGHT: (C)2005,JPO&NCIPI