TRIPLE REDUNDANCY ERROR CORRECTING CIRCUIT

PROBLEM TO BE SOLVED: To obtain a triple redundancy error correcting circuit which has smaller circuit scale than before and can detect a bit error even if a plurality of bit errors occur in the same system. SOLUTION: An error-corrected parallel output data 12 is obtained by using: shift registers 2...

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1. Verfasser: OKAWA FUTOSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To obtain a triple redundancy error correcting circuit which has smaller circuit scale than before and can detect a bit error even if a plurality of bit errors occur in the same system. SOLUTION: An error-corrected parallel output data 12 is obtained by using: shift registers 2a, 2b, and 2c which have both an input/output function for parallel data and an input/output function for bit data of shifting the parallel data, bit by bit; and a 1-bit width, three-system input type error correcting circuit 6, and by employing constitution in which error correction result detected by the error correcting circuit 6 is fed back as a series data input 8 of the shift register 2a. Thus, the triple redundancy error correcting circuit is obtained which has smaller circuit scale than before and can detect a bit error even if a plurality of bit errors occur in the same system. COPYRIGHT: (C)2005,JPO&NCIPI