TOOL FLOW PROCESS FOR PHYSICAL DESIGN OF INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a circuit design flow process which works properly with a large-scale ASIC chip design. SOLUTION: The circuit design flow process includes generating a netlist of a mapped gate level, generating netlist of the gate level through stages of a test facilitation design (...

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Hauptverfasser:	HELDER EDWARD R, UNSAL GUN, WEAVER JR EDWARD G
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide a circuit design flow process which works properly with a large-scale ASIC chip design. SOLUTION: The circuit design flow process includes generating a netlist of a mapped gate level, generating netlist of the gate level through stages of a test facilitation design (DFT (design-for-test)) and a clock tree construction, using the netlist generated as a result. Accordingly, reproducibility is guaranteed, by laying an important electrical infrastructure on an integrated circuit (IC), in advance, and use of the netlist generated as a result is also included. COPYRIGHT: (C)2005,JPO&NCIPI