SEMICONDUCTOR INTEGRATED CIRCUIT AND VOLTAGE BOOSTING METHOD USING SAME

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that has no parasitic motion such as latch-up and outputs a DC voltage boosted by a clock input signal, and a voltage boosting method using the same. SOLUTION: The voltage boosting circuit comprises: a first boosting circuit part 1a...

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Hauptverfasser: HINAKO TAKESHI, MIURA HIRONORI, AMANO KATSUMOTO, TANABE TAKESHI, TAKASE HIDEKI, SATO JUN, ITO YUICHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that has no parasitic motion such as latch-up and outputs a DC voltage boosted by a clock input signal, and a voltage boosting method using the same. SOLUTION: The voltage boosting circuit comprises: a first boosting circuit part 1a composed of a diode-connected transistor TR1 and a capacitor C1; a second boosting circuit part 1b composed of a diode-connected transistor TR2 and a capacitor C2; a (n-1)th boosting circuit part 1c composed of a diode-connected transistor TRN-1 and a capacitor CN-1; an n-th boosting circuit part 1d composed of a diode-connected transistor TRN; and a charge pump boosting circuit 2 composed of counters 3, 4. COPYRIGHT: (C)2005,JPO&NCIPI