CHIP CARRIER HAVING OPTIMIZED CIRCUITIZATION PATTERN

CHIP CARRIER HAVING OPTIMIZED CIRCUITIZATION PATTERN

PROBLEM TO BE SOLVED: To provide an electronic package, such as a chip carrier, with an optimized circuit pattern, which has a circuitized substrate on which first and second circuit patterns are formed. SOLUTION: The circuitized substrate includes a corner surface region. A second circuit pattern i...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: INFANTOLINO WILLIAM, ALCOE DAVID J, JADHAV VIRENDRA R
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide an electronic package, such as a chip carrier, with an optimized circuit pattern, which has a circuitized substrate on which first and second circuit patterns are formed. SOLUTION: The circuitized substrate includes a corner surface region. A second circuit pattern is electrically connected to a first circuit pattern on the corner surface region of the circuitized substrate and is positioned, in such a manner that cracks in the first circuit pattern are substantially inhibited during flexure of the chip carrier. COPYRIGHT: (C)2005,JPO&NCIPI