LOGICAL VERIFICATION DEVICE AND METHOD, RECORDING MEDIUM AND PROGRAM
PROBLEM TO BE SOLVED: To provide a logical verification device and method for shortening logical verification time by avoiding to repeat the same processing several times by using the same simulator. SOLUTION: An instruction level simulator 1 executes first instruction level simulation concerning a...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a logical verification device and method for shortening logical verification time by avoiding to repeat the same processing several times by using the same simulator. SOLUTION: An instruction level simulator 1 executes first instruction level simulation concerning a pre-processing instruction group in a test program, and an instruction level simulation result storing part 3 stores the execution result. A logic simulator 4 and an instruction level simulator 1 performs a simulation to execute an instruction group to be tested by using the execution result stored in the instruction level simulation result storing part 3. COPYRIGHT: (C)2004,JPO&NCIPI |
---|