LOGICAL VERIFICATION DEVICE AND METHOD, RECORDING MEDIUM AND PROGRAM

PROBLEM TO BE SOLVED: To provide a logical verification device and method for shortening logical verification time by avoiding to repeat the same processing several times by using the same simulator. SOLUTION: An instruction level simulator 1 executes first instruction level simulation concerning a...

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1. Verfasser: SHIRATORI YUKO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a logical verification device and method for shortening logical verification time by avoiding to repeat the same processing several times by using the same simulator. SOLUTION: An instruction level simulator 1 executes first instruction level simulation concerning a pre-processing instruction group in a test program, and an instruction level simulation result storing part 3 stores the execution result. A logic simulator 4 and an instruction level simulator 1 performs a simulation to execute an instruction group to be tested by using the execution result stored in the instruction level simulation result storing part 3. COPYRIGHT: (C)2004,JPO&NCIPI