INSPECTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PROBLEM TO BE SOLVED: To provide a method for failure analysis of a semiconductor integrated circuit enabling an IDDQ test even in a greatly miniaturized process. SOLUTION: An LSI 1 is equipped with a signal input/output terminal 2, a power source potential supply terminal 3, a ground potential supply terminal 4, a substrate potential supply terminal 5 of an Nch transistor, and a substrate potential supply terminal 6 of a Pch transistor. The LSI 1 is inspected by an external current inspection circuit 200 at the IDDQ test time. A determination result on whether a value determined by subtracting the current flowing in substrate potential supply wiring 9 of the Pch transistor and in substrate potential supply wiring 10 of the Nch transistor from the current flowing in power source potential supply wiring 7 is higher or lower than a prescribed determination standard current value recorded in the power source current inspection circuit 200 is outputted by an inspection determination signal. COPYRIGHT: (C)2004,JPO&NCIPI