SEMICONDUCTOR DEVICE AND ITS MANUFACTURING PROCESS

PROBLEM TO BE SOLVED: To reduce variation in the parasitic capacitance between wirings by forming a space between the wirings. SOLUTION: A plurality of wirings 4a-4d are formed on a substrate, a first insulation film 3 is formed between and on the wirings, trenches 7b'-7d' are formed selec...

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1. Verfasser: SUNADA TAKESHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To reduce variation in the parasitic capacitance between wirings by forming a space between the wirings. SOLUTION: A plurality of wirings 4a-4d are formed on a substrate, a first insulation film 3 is formed between and on the wirings, trenches 7b'-7d' are formed selectively in the first insulation film 3 between the wirings, and a second insulation film 8 is formed on the first insulation film 3 wherein spaces 7b-7d occupy the inside of the trenches. A space can be formed between the wirings especially at such a part as the wirings are arranged densely. Vacuum or gas exists in that space and since the dielectric constant is significantly low as compared with that of an interlayer insulation film, parasitic capacitance between the wirings can be reduced. COPYRIGHT: (C)2004,JPO&NCIPI