HARDWARE/SOFTWARE CO-VALIDATION METHOD

PROBLEM TO BE SOLVED: To provide a hardware/software co-validation method capable of enabling the speed-up of simulation by enabling a C-based native code simulation without deteriorating the precision of timing verification. SOLUTION: This method is a method for co-validating the hardware and softw...

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Hauptverfasser: FURUWATARI TOSHIAKI, HIRAO TOMOYA, FUJIKAKE HIDEAKI, NISHI HIROAKI, NIIYA TAKAO, MURAOKA MICHIAKI, YAMASHITA HIROYUKI, OKUMA ATSUSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a hardware/software co-validation method capable of enabling the speed-up of simulation by enabling a C-based native code simulation without deteriorating the precision of timing verification. SOLUTION: This method is a method for co-validating the hardware and software of a semiconductor device comprising at least one target CPU and one OS by use of a host CPU. As a validation model, a Timed software part of C-based language description or host CUP binary code and a hardware part of C-based language description are inputted, a necessary compilation is executed to link them. A test bench is then inputted to perform the compilation. Each part is linked with the test bench to execute simulation, and the result is outputted. COPYRIGHT: (C)2004,JPO&NCIPI