PLL CIRCUIT

PLL CIRCUIT

PROBLEM TO BE SOLVED: To reduce jitters generated in an output clock as much as possible when a PLL circuit formed on a semiconductor chip is used as a clock multiplication circuit. SOLUTION: A power supply line connected to the respective circuit blocks of a reference oscillator, a phase comparator...

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Bibliographische Detailangaben
1. Verfasser: KANZAKI MINORU
Format: Patent
Sprache:eng
Schlagworte:
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To reduce jitters generated in an output clock as much as possible when a PLL circuit formed on a semiconductor chip is used as a clock multiplication circuit. SOLUTION: A power supply line connected to the respective circuit blocks of a reference oscillator, a phase comparator, a charge pump circuit, a frequency divider and an output buffer is separated from a power supply line connected to a voltage controlled oscillator. COPYRIGHT: (C)2004,JPO&NCIPI