MEMORY CONTROL CIRCUIT, MEMORY DEVICE, AND MICROCOMPUTER

PROBLEM TO BE SOLVED: To provide a memory control circuit which can powerfully prevent erroneous writing due to noise and power momentary break. SOLUTION: First and second latch circuits 11 and 12 storing "0" and "1" by resetting are disposed, and an output signal of the first latch circuit 11 is inputted to the second latch circuit 12. Register setting data is inputted to the first latch circuit 11 through a first gate 13 where an input signal is made to pass when the output signal of the second latch circuit 12 is "1", and "0" is outputted when the output signal of the second latch circuit 12 is "0". A write signal is supplied to a memory as a memory write signal through a second gate 14 making an input signal pass through only when the output signal of the first latch circuit 11 is "1". When register setting data is "0", the output signals of the first and second latch circuits 11 and 12 become "0", and a system becomes an erroneous writing preventing state where the write signal is prevented from being outputted to the memory until it is reset. COPYRIGHT: (C)2004,JPO&NCIPI