COPROCESSOR EXTENSION ARCHITECTURE BUILT BY USING NOVEL SPLINT-INSTRUCTION TRANSACTION MODEL

PROBLEM TO BE SOLVED: To provide an improved technique for extending or alternating a processor instruction set architecture. SOLUTION: The processor architecture uses a split-instruction transaction so as to supply an extension unit with an operand and an instruction and to retrieve results from the extension unit and supports an electrical interface for coupling a processor core to one or more than one coprocessor extension units executing a computational instruction. The generic instructions for sending an operation and data to the extension unit and/or retrieving data from the extension unit allow a new computational instruction to be introduced without regeneration of the processor architecture. Support for a plurality of extension units and/or a plurality of execution pipes within each extension unit, multi-cycle execution latencies and different execution latencies between or within the extension units, extension instruction predicates, and for handling result save/restore on the processor core install and the interrupt is included. COPYRIGHT: (C)2004,JPO