WIRING PATTERN GENERATION METHOD AND WIRING PATTERN GENERATION DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit applied with a proper wiring delay countermeasure, having desired characteristics. SOLUTION: After deciding arrangement positions of elements mounted in the semiconductor integrated circuit, a distance of a shortest route connecting...

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1. Verfasser: HARAGUCHI NORIYUKI
Format: Patent
Sprache:eng
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