WIRING PATTERN GENERATION METHOD AND WIRING PATTERN GENERATION DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit applied with a proper wiring delay countermeasure, having desired characteristics. SOLUTION: After deciding arrangement positions of elements mounted in the semiconductor integrated circuit, a distance of a shortest route connecting...

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1. Verfasser:	HARAGUCHI NORIYUKI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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creator	HARAGUCHI NORIYUKI
description	PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit applied with a proper wiring delay countermeasure, having desired characteristics. SOLUTION: After deciding arrangement positions of elements mounted in the semiconductor integrated circuit, a distance of a shortest route connecting the elements is found to calculate a provisional delay value, the provisional delay value and a required delay time in each wire are compared, the wiring is classified into cases as this result, positions and the number of used contacts in multilayer wiring are found such that the required delay value is realized, and a wiring pattern is generated on the basis of the found contact positions. COPYRIGHT: (C)2004,JPO
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subjects	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
title	WIRING PATTERN GENERATION METHOD AND WIRING PATTERN GENERATION DEVICE
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