CACHE MEMORY DEVICE

PROBLEM TO BE SOLVED: To validly use a cache by easily selecting the resident priority of a specific instruction even in a process for simultaneously advancing a plurality of processes other than a single task. SOLUTION: This cache memory having data memory areas 200a and 200b in which data from a m...

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Bibliographische Detailangaben
1. Verfasser: KAMEMARU TOSHIHISA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To validly use a cache by easily selecting the resident priority of a specific instruction even in a process for simultaneously advancing a plurality of processes other than a single task. SOLUTION: This cache memory having data memory areas 200a and 200b in which data from a main memory are temporarily stored based on the instruction of a processor and tag memory areas 202a and 202b in which the addresses of the temporarily stored data are stored is provided with a process information management table 211 in which attributes including an identification number and cache resident priority are applied to each process indicating a series of execution of a program, and stored as a table. The tag memory area is provided with a column for designating the identification number corresponding to the process, and when the process is executed, the cache is used according to the processing of the designated attributes based on the identification number. COPYRIGHT: (C)2004,JPO