METHOD FOR DESIGNING INTEGRATED CIRCUIT HAVING SCAN FUNCTION
PROBLEM TO BE SOLVED: To provide a method for designing an integrated circuit having a logical circuit with a scan circuit without creating a hard macro library of a scan flip-flop constituting a scan circuit. SOLUTION: The system lays out a third netlist NL3 of hard macro only, temporarily obtains...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a method for designing an integrated circuit having a logical circuit with a scan circuit without creating a hard macro library of a scan flip-flop constituting a scan circuit. SOLUTION: The system lays out a third netlist NL3 of hard macro only, temporarily obtains sequence data of connection wiring for a scan chain, and lays out and implements automatic arrangement to a fifth netlist NL5 composed of a standard cell from a fourth netlist NL4 which has been formed with the sequence data. This realizes designing of the integrated circuit which can be laid out without using the layout library of the second flip-flop with a scan function. COPYRIGHT: (C)2004,JPO |
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