HIGH VOLTAGE VERTICAL TYPE DMOS TRANSISTOR, AND METHOD FOR PRODUCING THE SAME

PROBLEM TO BE SOLVED: To provide a method and a structure in which the vertical type DMOS as a typical high voltage operation transistor is effectively subjected to element separation, and at the same time, drain-source on-resistance is decreased. SOLUTION: A buried layer is formed on a semiconducto...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LEE SOOOL, SHIN WAJO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a method and a structure in which the vertical type DMOS as a typical high voltage operation transistor is effectively subjected to element separation, and at the same time, drain-source on-resistance is decreased. SOLUTION: A buried layer is formed on a semiconductor substrate and then a trench for element separation is formed and filled with an insulating film. Next, an epitaxial layer is grown on the film, and then etched to a depth to the buried layer, thereby a trench for drain is formed. An insulating film spacer is formed on a side wall of the trench adjacent to an element separation film, and then the trench is buried in a conductor to form a plug type drain, and a gate and a source are formed on the epitaxial layer. Thus, the drain-source on resistance is decreased, thereby a current increasing effect is obtained, and area of the element separation film is effectively reduced by using an existing element separation film, resulting in reduction of the chip area. COPYRIGHT: (C)2004,JPO