DESIGN METHOD OF TEST CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT
PROBLEM TO BE SOLVED: To minimize wirings used exclusively to test between the physical layers, when designing a test circuit for a single unit of function blocks to be built, in an integrated semiconductor circuit. SOLUTION: The exclusive wiring is made minimum for testing between the physical laye...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROBLEM TO BE SOLVED: To minimize wirings used exclusively to test between the physical layers, when designing a test circuit for a single unit of function blocks to be built, in an integrated semiconductor circuit. SOLUTION: The exclusive wiring is made minimum for testing between the physical layers, by disposing a selector circuit in each physical layer, using the terminals of actual operation rout to connect the isolation test output terminal to the outside terminals, and adding exclusive wiring only for the connection described in the test information but not described in the actual operation route of the net list, according to a net list describing the connection of the actual operation rout of the function blocks on the basis of the physical layers after the floor plan is carried out, and the test information describing the relations of the outer terminals and the isolation test output terminals of the function block requiring the isolation test. COPYRIGHT: (C)2004,JPO |
---|