METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT

METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT

PROBLEM TO BE SOLVED: To provide a method of forming a selection line for a NAND flash memory, which can improve the electric characteristics by minimizing the voltage drop, while simplifying the forming steps by eliminating the step of removing the dielectric film electrically connecting the floati...

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1. Verfasser: BOKU HEISHU
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Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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description PROBLEM TO BE SOLVED: To provide a method of forming a selection line for a NAND flash memory, which can improve the electric characteristics by minimizing the voltage drop, while simplifying the forming steps by eliminating the step of removing the dielectric film electrically connecting the floating gate and the control gate. SOLUTION: The floating gate is formed in a self-aligning etching process by patterning for forming a first projection at the edge of the control gate in a selection line composed of lamination of the floating gate, dielectric film and the control gate. After patterning the floating gate so that a second projection is formed overlapping the first projection at the edge of the floating gate, the first and the second projections are connected electrically using a contact plug and a metal wire to apply the same voltage to the low resistance control gate and the floating gate. COPYRIGHT: (C)2004,JPO
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2004048007A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2004048007A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2004048007A3</originalsourceid><addsrcrecordid>eNrjZLDzdQ3x8HdR8HdTcPMP8vX0c1cIdvVxdQ7x9PdT8PH0cwUJK_g5-rkouPk4Bnso-Lr6-gdFKgDV-Lr6hfAwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDAxMDEwsDA3NHY6IUAQCHeSo6</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT</title><source>esp@cenet</source><creator>BOKU HEISHU</creator><creatorcontrib>BOKU HEISHU</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a method of forming a selection line for a NAND flash memory, which can improve the electric characteristics by minimizing the voltage drop, while simplifying the forming steps by eliminating the step of removing the dielectric film electrically connecting the floating gate and the control gate. SOLUTION: The floating gate is formed in a self-aligning etching process by patterning for forming a first projection at the edge of the control gate in a selection line composed of lamination of the floating gate, dielectric film and the control gate. After patterning the floating gate so that a second projection is formed overlapping the first projection at the edge of the floating gate, the first and the second projections are connected electrically using a contact plug and a metal wire to apply the same voltage to the low resistance control gate and the floating gate. COPYRIGHT: (C)2004,JPO</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040212&amp;DB=EPODOC&amp;CC=JP&amp;NR=2004048007A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040212&amp;DB=EPODOC&amp;CC=JP&amp;NR=2004048007A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOKU HEISHU</creatorcontrib><title>METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT</title><description>PROBLEM TO BE SOLVED: To provide a method of forming a selection line for a NAND flash memory, which can improve the electric characteristics by minimizing the voltage drop, while simplifying the forming steps by eliminating the step of removing the dielectric film electrically connecting the floating gate and the control gate. SOLUTION: The floating gate is formed in a self-aligning etching process by patterning for forming a first projection at the edge of the control gate in a selection line composed of lamination of the floating gate, dielectric film and the control gate. After patterning the floating gate so that a second projection is formed overlapping the first projection at the edge of the floating gate, the first and the second projections are connected electrically using a contact plug and a metal wire to apply the same voltage to the low resistance control gate and the floating gate. COPYRIGHT: (C)2004,JPO</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDzdQ3x8HdR8HdTcPMP8vX0c1cIdvVxdQ7x9PdT8PH0cwUJK_g5-rkouPk4Bnso-Lr6-gdFKgDV-Lr6hfAwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDAxMDEwsDA3NHY6IUAQCHeSo6</recordid><startdate>20040212</startdate><enddate>20040212</enddate><creator>BOKU HEISHU</creator><scope>EVB</scope></search><sort><creationdate>20040212</creationdate><title>METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT</title><author>BOKU HEISHU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2004048007A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BOKU HEISHU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOKU HEISHU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT</title><date>2004-02-12</date><risdate>2004</risdate><abstract>PROBLEM TO BE SOLVED: To provide a method of forming a selection line for a NAND flash memory, which can improve the electric characteristics by minimizing the voltage drop, while simplifying the forming steps by eliminating the step of removing the dielectric film electrically connecting the floating gate and the control gate. SOLUTION: The floating gate is formed in a self-aligning etching process by patterning for forming a first projection at the edge of the control gate in a selection line composed of lamination of the floating gate, dielectric film and the control gate. After patterning the floating gate so that a second projection is formed overlapping the first projection at the edge of the floating gate, the first and the second projections are connected electrically using a contact plug and a metal wire to apply the same voltage to the low resistance control gate and the floating gate. COPYRIGHT: (C)2004,JPO</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD OF FORMING SELECTION LINE FOR NAND FLASH MEMORY ELEMENT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T14%3A00%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BOKU%20HEISHU&rft.date=2004-02-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2004048007A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true