SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To achieve stable working and realize reduction of working irregularity on a manufacturing process by ensuring area ratio and peripheral length of a dummy pattern of a wiring system and arranging a dummy pattern of a contact hole. SOLUTION: A mesh type (hole type) dummy pattern...

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Hauptverfasser: HIRANO HIROSHIGE, SAKAGAMI MASAHIKO
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator HIRANO HIROSHIGE
SAKAGAMI MASAHIKO
description PROBLEM TO BE SOLVED: To achieve stable working and realize reduction of working irregularity on a manufacturing process by ensuring area ratio and peripheral length of a dummy pattern of a wiring system and arranging a dummy pattern of a contact hole. SOLUTION: A mesh type (hole type) dummy pattern is used as the wiring system dummy pattern, and the area ratio and the peripheral length which are necessary in small area are maintained. The wiring system first dummy pattern 2a of a first wiring layer, the wiring system second dummy pattern 4a of a second wiring layer, and the dummy pattern 5 of the contact hole which connects the first and the second dummy patterns, are arranged, so that working irregularity on a manufacturing process is reduced. Separation of a usual pattern and the dummy pattern is made greater than the minimum separation of the usual pattern, so that wiring capacity is reduced. COPYRIGHT: (C)2004,JPO
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2004031636A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2004031636A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2004031636A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBiYGxoZmxmaOxkQpAgC8AR8Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>HIRANO HIROSHIGE ; SAKAGAMI MASAHIKO</creator><creatorcontrib>HIRANO HIROSHIGE ; SAKAGAMI MASAHIKO</creatorcontrib><description>PROBLEM TO BE SOLVED: To achieve stable working and realize reduction of working irregularity on a manufacturing process by ensuring area ratio and peripheral length of a dummy pattern of a wiring system and arranging a dummy pattern of a contact hole. SOLUTION: A mesh type (hole type) dummy pattern is used as the wiring system dummy pattern, and the area ratio and the peripheral length which are necessary in small area are maintained. The wiring system first dummy pattern 2a of a first wiring layer, the wiring system second dummy pattern 4a of a second wiring layer, and the dummy pattern 5 of the contact hole which connects the first and the second dummy patterns, are arranged, so that working irregularity on a manufacturing process is reduced. Separation of a usual pattern and the dummy pattern is made greater than the minimum separation of the usual pattern, so that wiring capacity is reduced. COPYRIGHT: (C)2004,JPO</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040129&amp;DB=EPODOC&amp;CC=JP&amp;NR=2004031636A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040129&amp;DB=EPODOC&amp;CC=JP&amp;NR=2004031636A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIRANO HIROSHIGE</creatorcontrib><creatorcontrib>SAKAGAMI MASAHIKO</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To achieve stable working and realize reduction of working irregularity on a manufacturing process by ensuring area ratio and peripheral length of a dummy pattern of a wiring system and arranging a dummy pattern of a contact hole. SOLUTION: A mesh type (hole type) dummy pattern is used as the wiring system dummy pattern, and the area ratio and the peripheral length which are necessary in small area are maintained. The wiring system first dummy pattern 2a of a first wiring layer, the wiring system second dummy pattern 4a of a second wiring layer, and the dummy pattern 5 of the contact hole which connects the first and the second dummy patterns, are arranged, so that working irregularity on a manufacturing process is reduced. Separation of a usual pattern and the dummy pattern is made greater than the minimum separation of the usual pattern, so that wiring capacity is reduced. COPYRIGHT: (C)2004,JPO</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBiYGxoZmxmaOxkQpAgC8AR8Q</recordid><startdate>20040129</startdate><enddate>20040129</enddate><creator>HIRANO HIROSHIGE</creator><creator>SAKAGAMI MASAHIKO</creator><scope>EVB</scope></search><sort><creationdate>20040129</creationdate><title>SEMICONDUCTOR DEVICE</title><author>HIRANO HIROSHIGE ; SAKAGAMI MASAHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2004031636A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HIRANO HIROSHIGE</creatorcontrib><creatorcontrib>SAKAGAMI MASAHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIRANO HIROSHIGE</au><au>SAKAGAMI MASAHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2004-01-29</date><risdate>2004</risdate><abstract>PROBLEM TO BE SOLVED: To achieve stable working and realize reduction of working irregularity on a manufacturing process by ensuring area ratio and peripheral length of a dummy pattern of a wiring system and arranging a dummy pattern of a contact hole. SOLUTION: A mesh type (hole type) dummy pattern is used as the wiring system dummy pattern, and the area ratio and the peripheral length which are necessary in small area are maintained. The wiring system first dummy pattern 2a of a first wiring layer, the wiring system second dummy pattern 4a of a second wiring layer, and the dummy pattern 5 of the contact hole which connects the first and the second dummy patterns, are arranged, so that working irregularity on a manufacturing process is reduced. Separation of a usual pattern and the dummy pattern is made greater than the minimum separation of the usual pattern, so that wiring capacity is reduced. COPYRIGHT: (C)2004,JPO</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T09%3A06%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HIRANO%20HIROSHIGE&rft.date=2004-01-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2004031636A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true