DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN
PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with...
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creator | AKAHA MASASHI |
description | PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with circuit information for a targeted circuit, a second storage part 12 stored with group classification information (group information) for classifying external terminals of a non-scanning test circuit, a third storage part 13 stored with library information of a BS cell, a fourth storage part 14 stored with connection rule information for the BS cell, a fifth storage part 15 stored with test pattern information for the targeted circuit, and a sixth storage part 16 stored with protocol information for boundary scanning test. A prescribed data processing program is executed in the data processing part 10, based on the informations stored in the first - the sixth storage parts 11-16. COPYRIGHT: (C)2004,JPO |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2003308349A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2003308349A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2003308349A3</originalsourceid><addsrcrecordid>eNrjZGh2cQ3zdHZVcPMPUggIcg1wDPL0c1dw9gxyDvUM0VHAKhviGhyiEOAYEuIa5IeiJDg0IMA_KASkxsU12NMdKOvo56Lg6xri4e-i4O-GwwweBta0xJziVF4ozc2g5OYa4uyhm1qQH59aXJCYnJqXWhLvFWBkYGBsbGBhbGLpaEyUIgBqsD0s</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN</title><source>esp@cenet</source><creator>AKAHA MASASHI</creator><creatorcontrib>AKAHA MASASHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with circuit information for a targeted circuit, a second storage part 12 stored with group classification information (group information) for classifying external terminals of a non-scanning test circuit, a third storage part 13 stored with library information of a BS cell, a fourth storage part 14 stored with connection rule information for the BS cell, a fifth storage part 15 stored with test pattern information for the targeted circuit, and a sixth storage part 16 stored with protocol information for boundary scanning test. A prescribed data processing program is executed in the data processing part 10, based on the informations stored in the first - the sixth storage parts 11-16. COPYRIGHT: (C)2004,JPO</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031031&DB=EPODOC&CC=JP&NR=2003308349A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031031&DB=EPODOC&CC=JP&NR=2003308349A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AKAHA MASASHI</creatorcontrib><title>DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN</title><description>PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with circuit information for a targeted circuit, a second storage part 12 stored with group classification information (group information) for classifying external terminals of a non-scanning test circuit, a third storage part 13 stored with library information of a BS cell, a fourth storage part 14 stored with connection rule information for the BS cell, a fifth storage part 15 stored with test pattern information for the targeted circuit, and a sixth storage part 16 stored with protocol information for boundary scanning test. A prescribed data processing program is executed in the data processing part 10, based on the informations stored in the first - the sixth storage parts 11-16. COPYRIGHT: (C)2004,JPO</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZGh2cQ3zdHZVcPMPUggIcg1wDPL0c1dw9gxyDvUM0VHAKhviGhyiEOAYEuIa5IeiJDg0IMA_KASkxsU12NMdKOvo56Lg6xri4e-i4O-GwwweBta0xJziVF4ozc2g5OYa4uyhm1qQH59aXJCYnJqXWhLvFWBkYGBsbGBhbGLpaEyUIgBqsD0s</recordid><startdate>20031031</startdate><enddate>20031031</enddate><creator>AKAHA MASASHI</creator><scope>EVB</scope></search><sort><creationdate>20031031</creationdate><title>DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN</title><author>AKAHA MASASHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2003308349A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>AKAHA MASASHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AKAHA MASASHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN</title><date>2003-10-31</date><risdate>2003</risdate><abstract>PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with circuit information for a targeted circuit, a second storage part 12 stored with group classification information (group information) for classifying external terminals of a non-scanning test circuit, a third storage part 13 stored with library information of a BS cell, a fourth storage part 14 stored with connection rule information for the BS cell, a fifth storage part 15 stored with test pattern information for the targeted circuit, and a sixth storage part 16 stored with protocol information for boundary scanning test. A prescribed data processing program is executed in the data processing part 10, based on the informations stored in the first - the sixth storage parts 11-16. COPYRIGHT: (C)2004,JPO</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
title | DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN |
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