DEVICE FOR PREPARING CIRCUIT, DEVICE FOR PREPARING TEST PATTERN, DEVICE FOR SUPPORTING DESIGN, AND METHOD OF PREPARING TEST PATTERN

PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: AKAHA MASASHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To reduce the number of test patterns and a test time for a boundary scanning register. SOLUTION: This device is constituted of a data processing part 10 and a plurality of information storage parts, and the information storage parts includes a first storage part 11 stored with circuit information for a targeted circuit, a second storage part 12 stored with group classification information (group information) for classifying external terminals of a non-scanning test circuit, a third storage part 13 stored with library information of a BS cell, a fourth storage part 14 stored with connection rule information for the BS cell, a fifth storage part 15 stored with test pattern information for the targeted circuit, and a sixth storage part 16 stored with protocol information for boundary scanning test. A prescribed data processing program is executed in the data processing part 10, based on the informations stored in the first - the sixth storage parts 11-16. COPYRIGHT: (C)2004,JPO