MULTIPROCESSOR SYSTEM AND NODE DEVICE

PROBLEM TO BE SOLVED: To provide a multiprocessor system capable of reducing unnecessary cache coincidence control and an inter-node access by the control. SOLUTION: This system is constituted by connecting a plurality of nodes 100 and 200 having one or more processors each of which has a cache memory and memories. Each node has directories 150 and 250 for registering information on data in a memory within the present node registered in a cache memory of an other node and node controllers 140 and 240 for specifying a node requiring a cache coincidence control based on information registered in the directories 150 and 250. The information registered in the directories 150 and 250 is addresses of object data and registered states of object data in the other node. Each node has a means for deciding that data requested to be registered in the cache memory is an instruction code. When the data is the instruction code, the cache coincidence control is not performed. COPYRIGHT: (C)2003,JPO